最近公司人手不足，除了，出門跑客戶外，還要用Cadence HAL幫忙檢查每個IC designer的Verilog code ，真是蠟燭兩頭燒。但也因此發現，大部分IC designer忙於加班趕進度，沒有力氣來充實本身design 功力，蠻可惜！所以，貢獻這篇在Synopsys SUNG-2000 Boston得到第二名的文章，希望對大家有幫助。

以下是該篇文章的Abstract和Introduction ：

標題：

Coding And Scripting Techniques For FSM Designs With Synthesis-Optimized, Glitch-Free Outputs

作者：Clifford E. Cummings

Abstract：A common synthesis recommendation is to code modules with a cloud of combinational logic on the module inputs and registered logic on all of the module outputs. FSM designs often include outputs generated from combinational logic based on the present state or combinational Mealy outputs. This paper details design and synthesis techniques that support the coding and synthesis scripting of glitch-free registered outputs for Finite State Machine designs.

Introduction ：Efficient state machine design using a Hardware Description Language (HDL), such as Verilog, can take many forms [1][2]. Are there specific forms that lend themselves well to synthesis? This paper describes some common coding styles and highlights two coding styles with registered outputs that are well suited for commonly used synthesis techniques.

This paper will briefly describe coding styles that generate combinational logic outputs and then will detail coding styles that generate registered outputs and describe why the registered output coding styles are often beneficial to synthesis strategies.

由於blog空間有限，需要這篇文章的朋友，可以寫e-mail 向我索取，我的e-mail 信箱是icalias@outlook.com

~請用點擊廣告來鼓勵我的付出，謝謝~