雖然是一篇非常…非常「有歷史」的文章，而且Design Compiler 2000.11也是十三年前的版本，會與大家分享該篇文章的原因是在於 high-fanout circuit 觀念的說明，與synthesis 處理手法，希望對大家有幫助。

以下是該篇文章的Abstract和Introduction ：

標題：

High Fanout Without High Stress: Synthesis and

Optimization of High-fanout Nets Using Design Compiler 2000.11

作者：Rick Furtner (Tensilica, Inc)

Abstract：High fanout nets, especially resets and gated clock nets, typically result in long synthesis runtimes, and gives poor results. Fortunately, Design Compiler 2000.11 has added some improvements that can help designers overcome these problems. This paper will first show some of the problems caused by high fanout nets. Then, the new commands available in DC 2000.11 for improving the synthesis results of high-fanout nets will be discussed. Last, synthesis results on test circuits containing some large-fanout nets will be presented.

Introduction ：High fanout nets, especially resets and gated clock nets, typically result in long synthesis runtimes, and gives poor results. This is due to the disconnect between the pre-layout assumptions made by the static timing analyzer, and the actual post-layout circuit. This paper will focus on the disconnect between pre and post-layout high-fanout nets, and strategies to minimize this disconnect.

由於blog空間有限，需要這篇文章的朋友，可以寫e-mail 向我索取，我的e-mail 信箱是icalias@outlook.com

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