最近在整理IC design 相關文件，看到多年前當project leader of IC team所收集的文件，往事歷歷，尤其看到Motorola 的”Verilog HDL Coding - Semiconductor Reuse Standard” ，感觸頗深….

 Anyway! 這是有價值的規範，值得任何 IC designer 或 project leader 善加利用。以下是

 Introduction

The general coding standards pertain to IP/VC generation and deal with naming conventions, documentation of the code and the format, or style, of the code. Conformity to these standards simplifies reuse by describing insight that is absent from the code, making the code more readable and assuring compatibility with most tools. Any exceptions to the rules specified in this standard, except as noted, must be justified and documented.

 The methodology standards promote reuse by ensuring a high adaptability among applications. The intent of this document is to ensure that the gate level implementation is identical to the HDL code as it is understood by a standard Verilog simulator. Partitioning can affect the ease with which a model can be adapted to an application. The modeling complex behavior section deals with structures that are typically difficult to address well in a synthesis environment and are needed to ensure pre- and post-synthesis consistency. These standards apply to behavioral as well as synthesizable code.

These Verilog-centric standards were developed after an analysis of the Motorola design community, and are heavily based on the existing Module Board coding guidelines. However, several other sources were also considered, including VSIA, M-CORE, and Star12.

~如果需要這份Motorola文件，歡迎來函索取，我的e-mail 信箱是icalias@outlook.com

~請用點擊廣告來鼓勵我的付出，謝謝