最近公司的SoC在Xilinx platform 驗證，結果有問題發生，但是rtl simulation卻是OK的，追到最後，發現是cross two clock-domains的問題，其中原因是

「雖然兩個clock的頻率相同，但實際上，這兩個clock是來自不同的OSC，會有些微duration的差異，經過時間的累積後，造成rtl simulation OK，但FPGA verification fail的現象。」

過去，我常看到一些IC engineer會用以下解法來處理cross two clock-domains的問題：

「用頻率較快的clock，來sample頻率較慢的clock-domain data-bus。」

但是這樣的作法，會sample到data-bus 的transition state，所以要小心處理！

當然 ，如果「用頻率較慢的clock，來sample頻率較快的clock-domain data-bus」，鐵定fail！

依照多年的經驗，針對cross two clock-domains問題，發現最佳解法是「用asynchronous FIFO」，而且Synopsys 的DesignWare已經有現成的asynchronous FIFO (DW_fifo_s2_sf)可以使用，既容易又安全，值得大家多多利用。同時，貢獻這篇在Synopsys SUNG-2002 San Jose, CA得到第一名的文章，希望對大家有幫助。

以下是該篇文章的Abstract和Introduction ：

標題：

Simulation and Synthesis Techniques for Asynchronous

FIFO Design with Asynchronous Pointer Comparisons

作者：Clifford E. Cummings and Peter Alfke

Abstract：

An interesting technique for doing FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains that are asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. The asynchronous FIFO comparison method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper.

To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built-in binary ripple carry logic.

This FIFO design paper builds on information already presented in another FIFO design paper where the FIFO pointers are synchronized into the opposite clock domain before running "FIFO full" or "FIFO empty" tests. The reader may benefit from first reviewing the FIFO Style #1 method before proceeding to this FIFO Style #2 method.

Introduction ：

An asynchronous FIFO refers to a FIFO design where data values are written sequentially into a FIFO buffer using one clock domain, and the data values are sequentially read from the same FIFO buffer using another clock domain, where the two clock domains are asynchronous to each other.

One common technique for designing an asynchronous FIFO is to use Gray[4] code pointers that are synchronized into the opposite clock domain before generating synchronous FIFO full or empty status signals[1]. An interesting and different approach to FIFO full and empty generation is to do an asynchronous comparison of the pointers and then asynchronously set the full or empty status bits[6].

This paper discusses the FIFO design style with asynchronous pointer comparison and asynchronous full and empty generation. Important details relating to this style of asynchronous FIFO design are included. The FIFO style implemented in this paper uses efficient Gray code counters, whose implementation is described in the next section.

由於blog空間有限，需要這篇文章的朋友，可以寫e-mail 向我索取，我的e-mail 信箱是icalias@outlook.com

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