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藉RTP製程抑制閘極側壁缺陷提升128M SDRAM良率
2018/04/07 12:05
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參考文獻:

https://avs.scitation.org/doi/abs/10.1116/1.1385917?journalCode=jvn

Sidewall oxidation behavior of dichlorosilane-based W-polycide gate

多晶矽化鎢閘極結構的製造方法 

一種避免閘極之矽化金屬層側壁產生突出物的方法  

Effect of annealing ambient on WSi x (x=2.3) sidewall deformation and contact resistance in dichlorosilane-based W-polycide gate

Monitoring and purging dynamics of trace gaseous impurity in atmospheric pressure rapid thermal process

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