FPGA - 使用Verilog設計SAP1(Control)
2014/12/24 13:56
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module top( opcode,decodeout1,decodeout2,decodeout3,clk,reset);
input[3:0] opcode;
input clk,reset;
output[6:0] decodeout1,decodeout2,decodeout3;//
wire [11:0] con;
wire[6:0] decodeout1,decodeout2,decodeout3,decodeout4;
wire clk_out;
//divider d( clk_out,clk_in,clr );
dik d(clk_out, clk, reset);
Control c( clk_out, reset, con, opcode);
LED M1(con[11:8],decodeout1);
LED M2(con[7:4],decodeout2);
LED M3(con[3:0],decodeout3);
endmodule
module Control(clk, reset, con, opcode);
input clk,reset;
input [3:0] opcode;
output [11:0] con;
reg [11:0] con;
reg[4:0] pre;
reg[4:0] next;
always @ (negedge clk or posedge reset)
begin
if (reset)
pre<=0;
else pre<=next;
end
always @ (opcode or pre)
case (pre)
//reset CLR
0: begin //T1
con = 12'h5E3;
next = 1;
end
1: begin //T2
con = 12'hBE3;
next = 2;
end
2: begin //T3
con = 12'h263;
if(opcode==0) //LDA
next=3;
else if(opcode==1) //ADD
next=6;
else if(opcode==2) //SUB
next=9;
else if(opcode==14) //OUT
next=12;
else if(opcode==15) //HLT
next=15;
else
next=0;
end
//LDA 0000
3:begin //T4
con = 12'h1A3;
next=4;
end
4:begin //T5
con = 12'h2C3;
next=5;
end
5: begin //T6
con = 12'h3E3;
next=0;
end
//ADD 0001
6: begin //T7
con = 12'h1A3;
next=7;
end
7:begin //T8
con = 12'h2E1;
next=8;
end
8:begin //T9
con = 12'h3C7;
next=0;
end
//SUB 0010
9:begin //T10
con = 12'h1A3;
next=10;
end
10: begin //T11
con = 12'h2E1;
next=11;
end
11: begin //T12
con = 12'h3CF;
next=0;
end
//OUT 1110
12:begin //T13
con = 12'h3F2;
next=13;
end
13: begin //T14
con = 12'h3E3;
next=14;
end
14: begin //T15
con = 12'h3E3;
next=0;
end
//HLT 1111
15:begin //T16
con = 12'h3E3;
next=16;
end
16: begin //T17
con = 12'h3E3;
next=17;
end
17:begin //T18
con = 12'h3E3;
next=0;
end
default: begin
con = 12'h5E3;
next = 1;
end
endcase
endmodule
module LED
(
q,
ledn
);
output ledn;
input[3:0] q;
reg [6:0] ledn;
wire [3:0] q;
always@(*)
begin
case(q)
4'b0000: ledn = 7'b1000000; //0
1: ledn = 7'b1111001; //1
2: ledn = 7'b0100100; //2
3: ledn = 7'b0110000; //3
4: ledn = 7'b0011001; //4
5: ledn = 7'b0010010; //5
6: ledn = 7'b0000010; //6
7: ledn = 7'b1111000; //7
8: ledn = 7'b0000000; //8
9: ledn = 7'b0010000; //9
10: ledn = 7'b000_1000; //A
11: ledn = 7'b000_0011; //B
12: ledn = 7'b100_0110; //C
13: ledn = 7'b010_0001; //D
14: ledn = 7'b000_0110; //e
15: ledn = 7'b000_1110; //f
default: ledn = 7'b00000; //0
endcase
end
endmodule
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