FPGA - 使用Verilog設計電子鐘
2014/12/19 11:45
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DIV3
module div3( q, reset, clk);
output q;
input clk,reset;
reg [1:0] next;
reg [1:0] q;
always @(negedge clk or posedge reset)
begin
if(reset) q <= 0="" div="">
else q <= next="" div="">
end
always @(*)
begin
case(q)
0: next = 1;
1: next = 2;
2: next = 0;
default : next = 0;
endcase
end
endmodule
--------------------------------------------------------------------------------------
DIV6
module div6( q, reset, clk);
output q;
input clk,reset;
reg [2:0] next;
reg [2:0] q;
always @(negedge clk or posedge reset)
begin
if(reset) q <= 0="" div="">
else q <= next="" div="">
end
always @(*)
begin
case(q)
0: next = 1;
1: next = 2;
2: next = 3;
3: next = 4;
4: next = 5;
5: next = 0;
default : next = 0;
endcase
end
endmodule
--------------------------------------------------------------------------------------
DIV10
module div10( q, reset, clk);
output q;
input clk,reset;
reg [3:0] next;
reg [3:0] q;
always @(negedge clk or posedge reset)
begin
if(reset) q <= 0="" div="">
else q <= next="" div="">
end
always @(*)
begin
case(q)
0: next = 1;
1: next = 2;
2: next = 3;
3: next = 4;
4: next = 5;
5: next = 6;
6: next = 7;
7: next = 8;
8: next = 9;
9: next = 0;
default : next = 0;
endcase
end
endmodule
--------------------------------------------------------------------------------------
divider
module divider( clk_out, clk_in, reset);
input clk_in,reset;
output clk_out;
wire reset;
reg [25:0] count;
always @( posedge clk_in or posedge reset )
begin
if(reset) count <= 0="" div="">
else count <= count="" 1="" div="">
end
assign clk_out = count[21]; //2^17
endmodule
--------------------------------------------------------------------------------------
7段顯示器(0-9)
module led7( LED, q);
output LED;
input q;
reg [6:0] LED;
wire [3:0] q;
always@(*)
begin
case(q)
0: LED = 7'b1000000; //0
1: LED = 7'b1111001; //1
2: LED = 7'b0100100; //2
3: LED = 7'b0110000; //3
4: LED = 7'b0011001; //4
5: LED = 7'b0010010; //5
6: LED = 7'b0000010; //6
7: LED = 7'b1111000; //7
8: LED = 7'b0000000; //8
9: LED = 7'b0010000; //9
default: LED = 7'b00000; //0
endcase
end
endmodule
--------------------------------------------------------------------------------------
topClock
module topClock(
hour_10,
hour_01,
minute_10,
minute_01,
clk,
out_reset
);
input clk,out_reset;
output hour_10,hour_01,minute_10,minute_01;
wire [1:0] hour_10;
wire [3:0] hour_01;
wire [2:0] minute_10;
wire [3:0] minute_01;
div10 d1( minute_01, reset, clk );
div6 d2( minute_10, reset, minute_01[3] );
div10 d3( hour_01, reset, minute_10[2] );
div3 d4( hour_10, reset, hour_01[3] );
assign out_and = hour_10[1] & hour_01[2];
assign reset = out_reset | out_and;
endmodule
--------------------------------------------------------------------------------------
topClock2
module topClock2(
LED1,
LED2,
LED3,
LED4,
out_reset,
clk
);
input clk,out_reset;
output LED1,LED2,LED3,LED4;
wire [1:0] hour_10;
wire [3:0] hour_01;
wire [2:0] minute_10;
wire [3:0] minute_01;
wire [6:0] LED1,LED2,LED3,LED4;
wire clk_out;
divider d( clk_out, clk, out_reset );
div10 d1( minute_01, reset, clk_out );
div6 d2( minute_10, reset, minute_01[3] );
div10 d3( hour_01, reset, minute_10[2] );
div3 d4( hour_10, reset, hour_01[3] );
led7 topled01( LED1, minute_01 );
led7 topled02( LED2, minute_10 );
led7 topled03( LED3, hour_01 );
led7 topled04( LED4, hour_10 );
assign out_and = hour_10[1] & hour_01[2];
assign reset = out_reset | out_and;
endmodule
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